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Languages - Verilog, VHDL, System C |
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Simulators - VCS, NC-Verilog, Modelsim, Aldec and Others |
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Analyzers - Debussy, Signal Scan and Others |
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Synthesis - Synopsys Design Compiler |
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Static Timing Analysis - Prime Time, Design Time |
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C, Perl, Make, Shell Programming |
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Formal Verification & Code Coverage Tools |
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Customer Specified Tools |
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