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Processor Cores
Network L2/L3 Switch Cores
DRAM Controllers
  - SDRAM Controller
  - DDR1 Controller
  - DDR2 Controller
Complete SoC Solutions
DRAM Controlers
DDR1 Controller
Support of AMBA AXI and AMBA AHB interfaces
Read and write FIFOs with configurable length
Configurable master system and memory bus width
Reordering function for maximum bandwidth
Supports DDR1, DDR2, FCRAM, RLDRAM memories
Fully programmable DRAM parameters
Dynamically reconfigurable memory burst length
Fully software based memory initialization and configuration
Built in self test
ECC - optional

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