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High-Performance cached MIPS I Instruction Set Compatible Processor
Core |
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Extensions and accelerators to the Instruction Set can be added |
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Two Staged Fully Pipelined Instruction Cache. The associativity
and size of Instruction Cache are configurable based on application
requirements. |
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Two Staged Fully Pipelined Data Cache. The associativity and
size of Data Cache are configurable based on application requirements. |
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250MHz Operating frequency in 0.18um TSMC process |
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Operating frequency can be increased if necessary. |
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0.3mm**2 in 0.18 TSMC process without memories |
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1.5mm**2 in 0.18 TSMC process including memories |
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Support for 3 external indepenedent memory systems, memory
load-store units included. |
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The External Memory Interface is scalable and it can support different
partitioning. |
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Gaskets can be added to support buses like AMBA etc. |
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RS232 based software debugger (optional) |
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Ideal for SoC data-communication, packet processors, packet classification
engines and embedded applications. |
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