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	Processor Cores Caches   - Direct-mapped Cache   - Set-Associative Cache   - Cache Controller Network L2/L3 Switch Cores DRAM Controllers Complete SoC Solutions		Caches Direct-mapped Cache Configurable Cache Line support for 4, 8, 16, 32 Word Cache-Lines Configurable Data Width supportf for 8, 16, 32, 64-bit Data Width Configurable number of Cache Lines - 32, 64, 128,, 256, 512,1024, 2048 Cache Lines supported Two-staged Fully Pipelined architecture AMBA AXI Memory Interface Support Stall And Flush Control Enabled Performance Optimization Features: Critical Word First Fetch Capability Cache-line Fetch Support With Address Wrap-around Capability Write-back Buffer For cache-line write-back optimization Suitable For Both Instruction And Data Memory Caches. product_brief.pdf
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