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Four-Way Set-Associative Cache (Configurable Architecture For
2, 4, 8-Way Set-Associative) |
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Configurable Cache Line support for 4, 8, 16, 32 Word Cache-
Lines |
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Configurable Data Width supportf for 8, 16, 32, 64-bit Data Width |
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Configurable number of Cache Lines per Bank - 32, 64, 128,, 256,
512 Cache Lines supported |
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Two-staged Fully Pipelined architecture |
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True Least-Recently Used (LRU) Replacement Policy . The replacement policy engine can be changed for area optimization. |
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AMBA AXI Memory Interface Support |
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Stall And Flush Control Enabled |
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Performance Optimization Features: |
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Critical Word First Fetch Capability |
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Cache-line Fetch Support With Address Wrap-around Capability |
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Write-back Buffer For cache-line write-back optimization |
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Suitable For Both Instruction And Data Memory Caches. |
