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Direct-Mapped, Set-Associative And Associative Cache Compatable |
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Configurable For Any Number Of Words Per Cache-Lines |
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Configurable For Any Number Of Cache Memory Banks |
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Configurable For 8, 16, 32, 64-bit Data Width |
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Configurable For Any Number Of Cache Lines |
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AMBA AXI Memory Interface Support |
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Other Interface Protocols Suport Can Be Added If `Needed |
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Performance Optimization Features: |
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Critical Word First Fetch Capability |
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Cache-line Fetch Support With Address Wrap-Around Capability |
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Write-back Buffer For Cache-Line Write-Back Optimization |
