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Processor Cores
  - Direct-mapped Cache
  - Set-Associative Cache
  - Cache Controller
Network L2/L3 Switch Cores
DRAM Controllers
Complete SoC Solutions
Cache Controller
Direct-Mapped, Set-Associative And Associative Cache Compatable
Configurable For Any Number Of Words Per Cache-Lines
Configurable For Any Number Of Cache Memory Banks
Configurable For 8, 16, 32, 64-bit Data Width
Configurable For Any Number Of Cache Lines
AMBA AXI Memory Interface Support
Other Interface Protocols Suport Can Be Added If `Needed
Performance Optimization Features:
Critical Word First Fetch Capability
Cache-line Fetch Support With Address Wrap-Around Capability
Write-back Buffer For Cache-Line Write-Back Optimization

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