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Processor Cores
  - Direct-mapped Cache
  - Set-Associative Cache
  - Cache Controller
Network L2/L3 Switch Cores
DRAM Controllers
Complete SoC Solutions
Set-Associative Cache
Four-Way Set-Associative Cache (Configurable Architecture For
2, 4, 8-Way Set-Associative)
Configurable Cache Line support for 4, 8, 16, 32 Word Cache-
Configurable Data Width supportf for 8, 16, 32, 64-bit Data Width
Configurable number of Cache Lines per Bank - 32, 64, 128,, 256,
512 Cache Lines supported
Two-staged Fully Pipelined architecture
True Least-Recently Used (LRU) Replacement Policy . The replacement policy engine can be changed for area optimization.
AMBA AXI Memory Interface Support
Stall And Flush Control Enabled
Performance Optimization Features:
Critical Word First Fetch Capability
Cache-line Fetch Support With Address Wrap-around Capability
Write-back Buffer For cache-line write-back optimization
Suitable For Both Instruction And Data Memory Caches.

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